Highly demanding photonic applications require the acquisition of images at very low light-level conditions and at high speed. Only Geiger mode CMOS imager, where the sensor in each pixel is Single Photon Avalanche Photodiode (SPADs), may meet the requirements for exceptional time resolution and ultimate optical sensitivity simultaneously. In spite of impressive progress, Geiger mode CMOS imagers with mega-pixels are still not available commercially.
It is known that a better insight in the evolution of the design and fabrication technology of SPADs up to the most recent results may be gained by looking at it in historical perspective, following the various reported designs and the two fabrication technologies, i.e., standard high-voltage CMOS (HV-CMOS) and dedicated CMOS-compatible technology.
Recent research efforts focus on integration of low-DCR SPADs in state of the art deep submicron CMOS processes and larger SPAD arrays with increasing levels of in-pixel and on-chip signal processing. Both efforts require further scaling of the CMOS SPAD technology as well as pixels, yet achieving high fill factor and low dark count rate (DCR) (below 100 Hz).
Various guard rings have been proposed to avoid edge breakdown. The earlier designs to prevent edge breakdown of a shallow p+-n junction were achieved by using a low-doped p− guard ring with a typical depth of a few microns, extending much deeper than the junction. This approach was implemented in CMOS technology as well, by implementing the active junction in n-well. This approach significantly reduces the effective fill factor and the Photon Detection Efficiency (PDE) since photo-carriers that reach the guard ring are not multiplied. Instead of employing a lightly doped p− diffused guard ring for reducing the field in the outer region, higher n+ doping was established in the central region for enhancing the electric field. Originally this design was implemented in double-epitaxial SPAD device structure and it has been extended to CMOS technology.
More recently, Finkelstein et al. reported a SPAD device fabricated in a low-voltage 0.18-μm CMOS technology. Edge breakdown is avoided in this device by bounding the active p+-n junction with shallow trench isolation (STI). However, the reported DCR is considerably high, most probably due to the derogative surface effects contributed by the STI surfaces, although it was attributed to strong tunneling and field-enhanced generation effects given the low breakdown voltage of the active junction (˜11 V).
It is easily seen that SPADs with conventional guard rings are characterized by effective low fill factor since the active region for multiplication is significantly smaller than the junction area. Hence, the reported low DCR in some of published papers may be attributed to the limited active area for multiplication and not necessarily to high performance. Furthermore, they cannot be scaled much below 5 μm because the depletion regions around the p-well implants expand and merge such that the active area of the SPAD is almost fully depleted. The SPAD then performs like a p-well n-well diode as the p+ n-well breakdown junction no longer operates.
Although 2-μm-active-diameter devices were reported using STI guard rings, hence increasing the fill factor, the dark count was extremely high (hundreds of kilohertz).
The introduction may be concluded by indicating that in spite of all the impressive progress reported in the literature, the reported designs cannot exhibit simultaneously high fill factor, high PDE, and low DCR. With the conventional guard rings, any photo carrier reaching the edges will not be detected since it will not trigger an avalanche. This is especially crucial for small diodes where the edges comprise a considerable portion of the junction area. Small pixels (less than ˜30 microns diameter) with small diodes are essential for SPAD arrays providing megapixels and high resolution. A completely new design is imperative in order to achieve SPAD imagers.